Lane G. Brooks

http://brooks.nu/~lane
lane -at- brooksee.org

Address: by request

Education - Massachusetts Institute of Technology

1999	B.S. in Electrical Engineering and Computer Science.	GPA 4.9/5.0
2000	M.Eng. in Electrical Engineering and Computer Science. Thesis: Amplitude and Frequency Demodulation Controller for MEMS Accelerometer	GPA 5.0/5.0
2008	Ph.D. in Electrical Engineering and Computer Science. Thesis: Design Techniques for Pipelined ADCs in Scaled CMOS Technologies	GPA 5.0/5.0

Work History

2005-	Independent Contractor: Hardware and software design services. IC Design: Custom IC design including analog circuit design, layout, verification, digital RTL development, simulation, synthesis, place and route, DFT, and chip finishing tasks. Hardware Design: PCB, FPGA, RTL (verilog and VHDL), simulation, and firmware design. Specialize in data acqusition systems. Software Development: Linux kernel drivers, firmware for embedded processors, test frameworks, signal processing, cross-platform GUI applications, and web design.	Highland, UT
2000-2005	SMaL Camera Technologies: Senior IC Design Engineer Led mixed-signal IC design for digital camera system. Architectural specification, verilog implementation, logic synthesis, place and route, timing verification, and DFT for still camera ASICs and integrated digital processing cores on imagers. Custom IC design including ADCs, DACs, regulators, transceivers, memory, and IOs. Firmware development for still camera models. Specialized in power efficient and highly integrated systems.	Cambridge, MA
2000	MIT: Teaching Assistant Head TA for 6.003 Signals and Systems course.	Cambridge, MA
1997-2000	Draper Laboratories: Intern and Draper Fellow Designed readout and controller logic for a vibratory MEMS accelerometers. Involved digital signal processing (filtering, demodulation, noise modeling) and feedback control in custom logic.	Cambridge, MA
1999	Prof. Charles Sodini of MIT: Undergraduate Researcher Implemented PC-based data acquisition system in Linux to display real-time, high frame rate data from CMOS imagers.	Cambridge, MA
1997-1998	Prof. Jesus del Alamo of MIT: Undergraduate Researcher Built web interface to an HP4155 Semiconductor Parameter Analyzer. Involved GP-IB, Java, and web development.	Cambridge, MA

Selected Patents (complete list at http://brooks.nu/~lane/pubs)

Aug 2002	Adaptive Sensitivity Control, on a pixel-by-pixel basis, for a Digital Imager	Pending
May 2004	Efficient digital method of and system for determining the instantaneous phase and amplitude of a vibratory accelerometer and other sensors	Pending
July 2004	In-stream Lossless Compression of Digital Image Sensor Data	Pending

Selected Publications (complete list at http://brooks.nu/~lane/pubs)

Jun 2004	Hardware Efficient Lossless Image Compression Engine	ICASSP
Feb 2006	A 3MPixel Low-Noise Flexible Architecture CMOS Image Sensor	ISSCC
Dec 2007	A Zero-Crossing Based 200MS/s 8b Pipelined ADC	JSSC
Nov 2008	Background Calibration of Pipelined ADCs Via Decision Boundary Gap Estimation.	TCAS-I
Dec 2009	A Fully Differential 12b, 50MS/s Zero-Crossing Based Pipelined ADC	JSSC

References and Sample Work

Available upon request.

Last Updated: Oct 2010